| 发明名称 |
Method for shape and timing equivalent dimension extraction |
| 摘要 |
An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
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| 申请公布号 |
US8037575(B2) |
申请公布日期 |
2011.10.18 |
| 申请号 |
US20080211624 |
申请日期 |
2008.09.16 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHENG YING-CHOU;LAI CHIH-MING;LIU RU-GUN;OU TSONG-HUA;WU MIN-HONG;DOONG YIH-YUH;CHAO HSIAO-SHU;CHENG YI-KAN;KU YAO-CHING;HOU CLIFF |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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