发明名称 Phase-locked loop
摘要 A phase-locked loop includes: a variable oscillator connected to a first resonator, said oscillator being able to deliver an output signal at a first output frequency Fout1, a first frequency divider receiving the output signal and able to convert it into a divided frequency signal Fout1/n, a reference oscillator connected to a second so-called reference resonator, delivering a reference signal at a low reference frequency Fref, generating an electrical dissipation lower than a microampere, a phase comparator measuring the phase error between the divided frequency signal Fout1/n and the reference signal and being able to produce a test signal, a low-pass filter or an integrating circuit able to filter the test signal and able to generate a voltage or a control word designed to control the voltage-controlled or digitally controlled oscillator.
申请公布号 US8040190(B2) 申请公布日期 2011.10.18
申请号 US20080113346 申请日期 2008.05.01
申请人 CSEM CENTRE SUISSE D'ELECTRONIQUE ET DE MICROTECHNIQUE SA-RECHERCHE ET DEVELOPPEMENT 发明人 RUFFIEUX DAVID
分类号 H03L7/00 主分类号 H03L7/00
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