发明名称 |
System and method for fetching information to a cache module using a write back allocate algorithm |
摘要 |
A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.
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申请公布号 |
US8041899(B2) |
申请公布日期 |
2011.10.18 |
申请号 |
US20080181701 |
申请日期 |
2008.07.29 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
GODIN KOSTANTIN;LANDA ROMAN;PELED ITAY;TOKAR YAKOV;ZAMSKY ZIV |
分类号 |
G06F12/00;G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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