| 摘要 |
Plural memory cell arrays laminated on the semiconductor substrate each includes a plurality of first wirings and second wirings formed to intersect with each other. The control circuit provides, in a non-selected second memory cell array that shares the first wiring with a selected first memory cell array, and a non-selected third memory cell array located more distant from the first memory cell array than the second memory cell array, the first potential to all of the first wirings and all of the second wirings. It also provides, in a non-selected fourth memory cell array that shares the second wiring with the first memory cell array and a non-selected fifth memory cell array located more distant from the first memory cell array than the fourth memory cell array, the second potential to all of the first wirings and all of the second wirings.
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