| 摘要 |
A system provides a cache memory coherency mechanism within a multi-processor computing system utilizing a shared memory space across the multiple processors. The system possesses a store address list for storing cache line addresses corresponding to a cache line write request issued by one of the multiple processors, a fetch address list for storing cache line addresses corresponding to a cache line fetch request issued by one of the multiple processors, a priority and pipeline module, a request tracker module and a read/write address list. The store address list and the fetch address list are queues containing result in cache lookup requests being done by the priority and pipeline module; and each entry in the store address list and the fetch address list possess status bits which indicate the state of the request.
|
