发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory device equipped with a new bit line hierarchization method enabling the power consumption of the semiconductor memory device to be further reduced.SOLUTION: The semiconductor memory device is equipped with: multiple memory blocks B provided in matrix configuration; and multiple main bit lines GL provided in association with the memory blocks B. The memory block B is equipped with: multiple memory cells C provided in matrix configuration; multiple sub bit lines BL provided for each column; multiple word lines WL provided for each column and row, and common to the multiple memory blocks B; and a switch circuit SC for connecting a corresponding main bit line GL to any of the multiple sub bit lines BL. In the reading operation of an object cell C1 as the object of read, a main bit line GL1 corresponding to the object cell C1 is selected, and a sub-bit line BL1 corresponding to a column of the object cell C1 is selected by the switch circuit SC1, then a word line WL1 corresponding to the column and the row of the object cell C1 is selected from among the multiple word lines WL.
申请公布号 JP2011204305(A) 申请公布日期 2011.10.13
申请号 JP20100069266 申请日期 2010.03.25
申请人 RENESAS ELECTRONICS CORP 发明人 KOBAYASHI YASUO
分类号 G11C16/06;G11C16/02;H01L21/8246;H01L27/112 主分类号 G11C16/06
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