发明名称 RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a receiver for improving an error generation rate and reducing a delay amount when attaining a target generation rate.SOLUTION: The receiver for inputting signals including random jitters whose generation probability is normally distributed with time, converting the input signals to digital data, and outputting them includes a clock circuit for generating a clock signal capable of setting a phase, a first reception circuit for converting the input signals to the digital data at timing based on the clock signals, outputting them and outputting error signals when an error is generated during the conversion, a second reception circuit for converting signals for which the input signals are delayed into digital data at the timing based on the clock signals, outputting them and outputting error signals when an error is generated during the conversion, and a data output control part for selecting and outputting the digital data from one of the first reception circuit and the second reception circuit on the basis of the error signals of the first and second reception circuits.
申请公布号 JP2011205366(A) 申请公布日期 2011.10.13
申请号 JP20100070250 申请日期 2010.03.25
申请人 YOKOGAWA ELECTRIC CORP 发明人 AOE TAKASHI
分类号 H04L7/02;H04L25/40 主分类号 H04L7/02
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