发明名称 READDRESSABLE VIRTUAL DMA CONTROL AND STATUS REGISTER
摘要 PROBLEM TO BE SOLVED: To provide a DMA controller that carries out DAM transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.SOLUTION: The DMA controller writes a value showing a transfer status of a data block from a source data location to a destination data location into a transfer status storage location, has a base address resister of the transfer status storage location. A control device writes a value specifying a base address of the transfer status storage location for each transfer into the base address resistor of the transfer status storage location. The base address of the transfer status storage location is different in at least part of the transfer. The base address of the transfer status storage location in a certain transfer is an address in a system memory. The base address of the transfer status storage location in other transfers is an address in a memory of another device.
申请公布号 JP2011204269(A) 申请公布日期 2011.10.13
申请号 JP20110134031 申请日期 2011.06.16
申请人 INTEL CORP 发明人 NI JIE;FUTRAL WILLIAM
分类号 G06F13/28 主分类号 G06F13/28
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