| 摘要 |
A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven.
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