SILICON WAFER ALIGNMENT METHOD APPLIED TO THROUGH SILICON VIA INTERCONNECTION

摘要

A silicon wafer alignment method is applied to through silicon via (TSV) interconnection. The method relates to high integration packaging technology field. When a plurality of silicon wafers are stacked and interconnected, the stacked upper and lower silicon wafers (2,3) are aligned by electrical method. Therefore, the precision of alignment of the silicon wafers can be enhanced, and the interconnection resistance can be reduced. The integrated circuit chip made by the method has performances of high speed and low power consumption.