| 摘要 |
<p>The invention relates to a cache memory (16') associated with a central memory (12) and with a processor (10) that can perform a data flow processing task, including a plurality of disjointed storage segments, each one of which is associated with a separate data category. A first segment is dedicated to the input data, said data coming from a flow of data consumed by the processing task. A second segment is dedicated to the output data, said data coming from a flow of data produced by the processing task. A third segment is dedicated to the global constants, corresponding to data that can be accessed at a single memory location at a plurality of instances of the processing task.</p> |
