发明名称 |
STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE |
摘要 |
A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.
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申请公布号 |
US2011249483(A1) |
申请公布日期 |
2011.10.13 |
申请号 |
US201113080061 |
申请日期 |
2011.04.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
OH CHI-SUNG;KIM JIN-HO;LEE HO-CHEOL;KANG UK-SONG;LEE HOON |
分类号 |
G11C5/06;G11C7/00 |
主分类号 |
G11C5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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