发明名称 Method and layout of semiconductor device with reduced parasitics
摘要 An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.
申请公布号 US8035140(B2) 申请公布日期 2011.10.11
申请号 US20070828944 申请日期 2007.07.26
申请人 INFINEON TECHNOLOGIES AG 发明人 BIRNER ALBERT;CHEN QIANG
分类号 H01L29/76 主分类号 H01L29/76
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