发明名称 |
Bist DDR memory interface circuit and method for testing the same |
摘要 |
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value.
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申请公布号 |
US8035407(B2) |
申请公布日期 |
2011.10.11 |
申请号 |
US201113079391 |
申请日期 |
2011.04.04 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
JARBOE, JR. JAMES MICHAEL;PANIGRAHI SUKANTA KISHORE;AGRAWAL VINAY;NAYAK NEERAJ P. |
分类号 |
G01R31/02 |
主分类号 |
G01R31/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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