发明名称 Clock and data recovery circuit
摘要 The phase detector compares the phases of a synchronous clock signal and serial data and outputs a phase error signal corresponding to a comparison result. The second integrator performs integration of the phase error signal to obtain a phase correction control signal for tracking phase shift of the serial data. The first integrator performs integration of the phase error signal in each smoothing period with a predetermined length to obtain a smoothed error signal. The pattern generator generates a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a predetermined length and outputs the pattern as a frequency correction control signal. The first integrator receives the frequency correction control signal which is fed back and changes the length of the smoothing period according to the direction of a change in the frequency of generating the frequency correction control signal.
申请公布号 US8036318(B2) 申请公布日期 2011.10.11
申请号 US20080078934 申请日期 2008.04.08
申请人 RENESAS ELECTRONICS CORPORATION 发明人 AOYAMA MORISHIGE
分类号 H04L27/00 主分类号 H04L27/00
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