| 摘要 |
An exemplary chip includes an input/output (I/O) area and a core area is provided. The input/output (I/O) area has a first I/O block operated under a first power domain and a second I/O block operated under a second power domain placed therein, wherein a voltage range of the first power domain is distinct from a voltage range of the second power domain. The core area has at least one circuit therein performing at least one function of the chip, and the core area further has at least one power cut cell placed therein wherein the power cut cell is coupled to the first I/O block and the second I/O block via a plurality of connectors for providing an electrostatic discharge (ESD) path between the first I/O block and the second I/O block.
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