发明名称 |
APPARATUS AND METHOD FOR REDUCING INTERFERENCE SIGNALS IN AN INTEGRATED CIRCUIT USING MULTIPHASE CLOCKS |
摘要 |
An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.
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申请公布号 |
US2011241747(A1) |
申请公布日期 |
2011.10.06 |
申请号 |
US20100752082 |
申请日期 |
2010.03.31 |
申请人 |
PRATHAPAN INDU;GHOSH ANJANA;BAISHYA DIGANTA;RANGACHARI SUNDARRAJAN;DEBNATH SANKAR PRASAD;DASH RANJIT KUMAR;RAMASWAMY SRINATH MATHUR |
发明人 |
PRATHAPAN INDU;GHOSH ANJANA;BAISHYA DIGANTA;RANGACHARI SUNDARRAJAN;DEBNATH SANKAR PRASAD;DASH RANJIT KUMAR;RAMASWAMY SRINATH MATHUR |
分类号 |
G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
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