发明名称 CLOCK SIGNALS FOR DYNAMIC RECONFIGURATION OF COMMUNICATION LINK BUNDLES
摘要 In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.
申请公布号 US2011246810(A1) 申请公布日期 2011.10.06
申请号 US200813133372 申请日期 2008.12.16
申请人 WESSEL ROBERT E;MARONI PETER D 发明人 WESSEL ROBERT E.;MARONI PETER D.
分类号 G06F1/08 主分类号 G06F1/08
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