| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit design method, shortening the verification period as compared with the conventional method.SOLUTION: In a processing (ST1), RTL (Register Transfer Level) data 32 described by the RTL and expressing a plurality of registers is generated using a hardware description language to a design specification 31 of a semiconductor integrated circuit. In a processing (ST2), according to an event 34 of data for verification, a virtual scan chain to which a scan object register group is connected is generated to form a shift register configuration (SI, SO, MD) using the scan object register group among the plurality of registers in the RTL data 32 and terminal information 35 (SI, SO, MD). In a processing (ST3), according to a test pattern 33 for verification and the event 34, simulation to the virtual scan chain is executed. When the execution result has a problem (ST4-NG), the processing (ST1) is again executed. |
