| 摘要 |
PROBLEM TO BE SOLVED: To provide a PMOS flash cell using a bottom poly control gate that can drastically reduce an area that a control gate occupies.SOLUTION: A two-transistor PMOS memory cell includes an SG-PMOS 150a, an FG-PMOS 150b, and the control gate 125. The SG-PMOS 150a has a drain and a source disposed in an n-type well 110. The FG-PMOS 150b has a drain and a source disposed in the n-type well 110. The drain of the SG-PMOS 150a and the source of the FG-PMOS 150b are the same. The control gate 125 is composed of a first polysilicon layer and formed on an isolation structure 115 and superimposed on an extending part of a floating gate 135b of the FG-PMOS 150b. |
