| 摘要 |
PROBLEM TO BE SOLVED: To provide a DLL circuit mounting a duty adjustment circuit that does not depend on the frequency of a clock signal.SOLUTION: The DLL circuit includes a delay line 110 that delays an internal clock signal ICLK to generate an internal clock signal LCLK, a counter circuit 123 that specifies an amount of delay of the delay line 110, a counter control circuit 122 that adjusts a count value of the counter circuit 123, and a subtraction circuit 133 that calculates a difference between first and second count values at which the rise edge of the internal clock signal ICLK coincides with that of a replica clock signal RepCLK. The fall edge of the internal clock signal LCLK is adjusted based on a value equivalent to 1/2 of the difference thus obtained. This prevents the applicable frequency range from being limited as with a case where a duty adjustment circuit of type that alternately discharges capacitors is used. |
