VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR, AND MULTIPROCESSOR SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a processor which can reduce a circuit volume by implementing functions of a TLB in a cache memory and has enhanced task switching responsiveness.SOLUTION: A virtual address cache memory includes: a TLB virtual page memory 21 rewrites entry data when a rewrite to the TLB occurs; a data memory 23 holds cache data using a virtual page tag or a page offset as a cache index; a cache state memory 24 holds a cache state for the cache data stored in the data memory in association with the cache index; a first physical address memory 22 rewrites a held physical address when the rewrite to the TLB occurs; and a second physical address memory 25 rewrites the held physical address when the cache data is written to the data memory after the occurrence of the rewrite to the TLB.