发明名称 Parallel processing architecture for video decompression
摘要 Disclosed herein is a video decoding system of a mobile broadcasting receiver. The video decoding system of a mobile broadcasting receiver for decoding a compression-coded video signal includes: at least one buffer memory for performing video decoding; a plurality of coprocessors including a data processing unit partitioned into one or more hardware blocks, wherein the data processing unit performs actual video decoding via data input/output from/to the buffer memory; and a DMA (Direct Memory Access) coprocessor for performing a direct access operation to an external memory, wherein, the at least one buffer memory, the plurality of coprocessors and the DMA coprocessor take the form of hardware, and operations thereof are controlled via software in a processor.
申请公布号 US8031772(B2) 申请公布日期 2011.10.04
申请号 US20050274289 申请日期 2005.11.16
申请人 LG ELECTRONICS INC. 发明人 KIM SANG CHUL
分类号 H04N7/12;G06K9/36 主分类号 H04N7/12
代理机构 代理人
主权项
地址