发明名称 |
Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values |
摘要 |
An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
|
申请公布号 |
US8031747(B2) |
申请公布日期 |
2011.10.04 |
申请号 |
US20090432630 |
申请日期 |
2009.04.29 |
申请人 |
JUNIPER NETWORKS, INC. |
发明人 |
BARRY CHARLES F.;SUBRAMANIAN MEENAKSHI S.;PAN FENG FRANK;SHEN TIAN (ALAN);KRUZINSKI PHILIP;ZHAO GUOCHUN (GEORGE);NATESAN DEVIPRASAD;JORGENSEN DAVID R. |
分类号 |
H04J3/06 |
主分类号 |
H04J3/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|