| 发明名称 |
Low read current architecture for memory |
| 摘要 |
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
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| 申请公布号 |
US8031545(B2) |
申请公布日期 |
2011.10.04 |
| 申请号 |
US20100799168 |
申请日期 |
2010.04.19 |
| 申请人 |
UNITY SEMICONDUCTOR CORPORATION |
发明人 |
RINERSON DARRELL;CHEVALLIER CHRISTOPHE;SIAU CHANG HUA |
| 分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
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