| 摘要 |
A semiconductor memory device configured to execute a standby operation for saving power during standby, and including a memory cell array including plural memory cells arranged at intersections of bit lines and word lines and storing cell data. A redundant memory cell array shares the bit lines with the memory cell array and includes plural redundant memory cells arranged at intersections of the bit lines and redundant word lines storing redundant data for error correction of cell data stored in the memory cell array. A sense amplifier senses and amplifies the voltage on the bit line to read the cell data or the redundant data from the memory cell array or the redundant memory cell array. A cyclic redundant encoder/decoder, through sequential processing, encodes the cell data to generate the redundant data, or decodes the cell data and the redundant data for error correction of the cell data.
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