| 摘要 |
A digital signal processing apparatus including: an arithmetic circuit that performs first digital signal processing on an input signal SA sampled at a first sampling frequency f1 and second digital signal processing on a result of the first digital signal processing; a timing control circuit that controls and causes the arithmetic circuit to perform the first and second digital signal processing; and a control circuit that monitors in real-time at least one of an amount of data subjected to the second digital signal processing and an amount of data to be transmitted by the input signal SA, and which controls the timing control circuit when the monitored data amount reaches a predetermined value.
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