| 摘要 |
A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.
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