| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a reception circuit for maintaining the number of samplings to one unit interval to be constant. <P>SOLUTION: The reception circuit includes a clock generation circuit (301) for generating a plurality of clock signals having different phases within one cycle, an oversampling circuit (303) for oversampling input data by the plurality of clock signals having different phases, a data boundary determination circuit (305) for detecting a time-series change point in digital data output from the oversampling circuit, and for determining two data boundaries at both ends of one unit interval, and a clock phase control circuit (306) for controlling the phase of the clock signal generated by the clock generation circuit so that the number of samplings of an adjacent one unit interval becomes constant when the number of samplings of one unit interval between the two determined data boundaries is larger than a threshold. <P>COPYRIGHT: (C)2011,JPO&INPIT |
