| 摘要 |
PROBLEM TO BE SOLVED: To process an interrupt event processing sequence, a branch event processing sequence, and a memory reference event processing sequence at high speed. SOLUTION: The semiconductor device includes a second storage part (104), a CPU core (103), and an exclusive bus (105). When an exception or interrupt event occurs, the CPU core accesses the second storage part via the exclusive bus, and acquires first address information of a processing routine for the exception or the interrupt corresponding to the exception or interrupt event. When a branch event occurs in response to a branch instruction or the like, the CPU core accesses the second storage part via the exclusive bus, and acquires a branch destination address corresponding to the event of a branch, and an instruction sequence or the like of a branch destination. When a memory reference event occurs in response to an operand reference instruction, the CPU core also accesses the second storage part via the exclusive bus, and acquires a memory reference destination address corresponding to the event of memory reference, and a reference destination data sequence or the like. COPYRIGHT: (C)2011,JPO&INPIT
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