发明名称 Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors
摘要 A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation occurring to the register renaming table, a determination is made as to whether an update to an entry in a hardware-implemented recovery renaming table is to be performed. If so, the entry in the hardware-implemented recovery renaming table is updated. The entry in the recovery renaming table is part of the checkpoint for the speculative execution of the portion of code.
申请公布号 US2011238962(A1) 申请公布日期 2011.09.29
申请号 US20100729282 申请日期 2010.03.23
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CAIN, III HAROLD W.;EKANADHAM KATTAMURI;PARK IL
分类号 G06F9/30 主分类号 G06F9/30
代理机构 代理人
主权项
地址