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发明名称
METHOD AND APPARATUS FOR PIPELINING ORDERED INPUT/OUTPUT TRANSACTIONS IN A CACHE COHERENT, MULTI-PROCESSOR SYSTEM
摘要
申请公布号
EP1311956(B1)
申请公布日期
2011.09.28
申请号
EP20010959749
申请日期
2001.08.14
申请人
INTEL CORPORATION
发明人
CRETA, KENNETH;LOOI, LILY;KUMAR, AKHILESH;KHARE, MANOJ
分类号
G06F12/08
主分类号
G06F12/08
代理机构
代理人
主权项
地址
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