发明名称 Test apparatus for a multi-task computing architecture and method therefor
摘要 <p>The device has a test generator (G) for generating sequences of test instructions (Pa,Pb,Pc,Pd) corresponding to programming rules for a computation architecture, where a controller is coupled to the test generator. The controller is provided for controlling parallel execution of the sequences of test instructions so that the sequences of test instructions are alternately executed. The controller synchronizes the alternate execution of the sequence of test instructions. Independent claims are also included for the following: (1) a method for testing a multi-tasking computation architecture; and (2) a computer program product for testing a multi-tasking computation architecture.</p>
申请公布号 EP2369487(A1) 申请公布日期 2011.09.28
申请号 EP20110157039 申请日期 2011.03.04
申请人 STMICROELECTRONICS (GRENOBLE 2) SAS 发明人 DE POY ALONSO, IKER
分类号 G06F11/263 主分类号 G06F11/263
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