| 摘要 |
A pulse sequence shaper with adjustable pulse length, period and fixed pause equal to two cycles comprises a reversible counterdown binary counter having a clock input, synchronous parallel load enable input, loading data inputs, counting mode enable input, asynchronous reset input, overflow output, an inverter, a circuit comprising in series connected resistor and capacitor, a start-stop device comprising a synchronous D flip-flop with asynchronous reset input, first and second two-input AND elements, two-input OR element. J-K flip-flops with J and K inverting inputs, having asynchronous reset input is incorporated. |
