发明名称 |
PHASE LOCKED LOOP CIRCUIT, LOCK DETECTING METHOD AND SYSTEM HAVING THE SAME |
摘要 |
Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal. |
申请公布号 |
KR20110105253(A) |
申请公布日期 |
2011.09.26 |
申请号 |
KR20100024402 |
申请日期 |
2010.03.18 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JANG, TAE KWANG;PARK, JAE JIN;KIM, JI HYUN |
分类号 |
H03L7/095;H03L7/08 |
主分类号 |
H03L7/095 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|