发明名称 |
PHASE-LOCKED LOOP CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, AND CONTROL METHOD OF PHASE-LOCKED LOOP CIRCUIT |
摘要 |
<P>PROBLEM TO BE SOLVED: To achieve improvement of a control response or reduction of power consumption in a phase-locked loop circuit. <P>SOLUTION: In both a pull-in step and a lock time, an oscillator controller 255 and a frequency divider controller 257 cause an oscillation control signal and a frequency division control signal to vary cooperatively with a proportional relationship on the basis of a loop filter voltage. An oscillating section 210 and a frequency dividing section 220 cooperatively operate both in the pull-in step and the lock time. The relationship of the control signals is set so that a peak operating frequency of the frequency dividing section 220 corresponding to any loop filter voltage both in the pull-in step and the lock time becomes higher than a frequency of an oscillation output signal of the oscillating section 210 at all the time. The frequency division control signal in the lock time automatically sets to the frequency dividing section 220 a bias current smaller than the bias current based on a loop filter signal corresponding to the peak frequency of the oscillation output signal of the oscillating section 210 in the pull-in step. Thus, power consumption in the lock time can be reduced. <P>COPYRIGHT: (C)2011,JPO&INPIT |
申请公布号 |
JP2011188183(A) |
申请公布日期 |
2011.09.22 |
申请号 |
JP20100050513 |
申请日期 |
2010.03.08 |
申请人 |
SONY CORP |
发明人 |
YAGISHITA YUKI;TSUKUDA YASUNORI |
分类号 |
H03L7/093;H03L7/08;H03L7/099;H03L7/183 |
主分类号 |
H03L7/093 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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