发明名称 WIRING BOARD AND SEMICONDUCTOR DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To suppress a decline of signal transmission characteristics due to plating stub wiring, without being restricted by a signal wiring layout. <P>SOLUTION: The wiring board 120 includes a signal wiring layer 130, and a ground or power supply plane 140 adjacent to the signal wiring layer 130 through an insulating layer. The signal wiring layer 130 includes two or more lines of signal wiring 132, electrically connected to the electrode pad 111a of a semiconductor element 111 and two or more lines of plating stub wiring 133, connected to the two or more lines of signal wiring 132. The ground or power supply plane 140 has an opening 145, facing the starting point part of each plating stub wiring which is the connection part of each plating stub wiring 133 with the signal wiring 132, and the characteristic impedance of the plating stub wiring 133 at the part is increased. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011187683(A) 申请公布日期 2011.09.22
申请号 JP20100051435 申请日期 2010.03.09
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 UENO SEIJI
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
主权项
地址