发明名称 |
MULTI-CORE PROCESSOR SYSTEM, ARBITRATION CIRCUIT CONTROL METHOD, AND ARBITRATION CIRCUIT CONTROL PROGRAM |
摘要 |
CPUs (S#1 - L#2) use an acquisition unit (304) to acquire an actual access speed value of each CPU to shared memory (203). Then, the CPUs (S#1 - L#2) use a response performance calculation unit (305) to calculate the CPU response performance of each CPU from the actual access speed value and a theoretical access speed value for the CPU. A CPU (L#3) uses an access ratio calculation unit (310) to calculate a shared memory (203) accessibility ratio for the plurality of CPUs so that the accessibility ratio of particular CPUs is higher than the accessibility ratio of CPUs having a higher response performance than the particular CPUs. The CPU (L#3) uses a notification unit (311) to notify an arbitration circuit (204) of the calculated accessibility ratio. |
申请公布号 |
WO2011114496(A1) |
申请公布日期 |
2011.09.22 |
申请号 |
WO2010JP54709 |
申请日期 |
2010.03.18 |
申请人 |
FUJITSU LIMITED;YAMASHITA, KOICHIRO;YAMAUCHI, HIROMASA |
发明人 |
YAMASHITA, KOICHIRO;YAMAUCHI, HIROMASA |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|