| 摘要 |
PROBLEM TO BE SOLVED: To provide techniques that shorten the delay time taken until an output logic is determined in a latch circuit. SOLUTION: The latch circuit includes: a first differential pair; a second differential pair; a third differential pair; and a bias current generating part. The first differential pair controls a current which is from a first resistance connected to a positive power-supply terminal, and a current which is from a second resistance connected to the positive power-supply terminal, based on a voltage between a pair of data input terminals. The second differential pair controls the current from the first resistance and the current from the second resistance based on the result of control carried out by the first differential pair. The third differential pair causes a bias current to flow to either one of the first differential pair and the second differential pair based on a voltage between a pair of clock input terminals. The bias current generating part generates a bias current so that, with respect to a predetermined range including positive/negative voltages, the bias current of the case in which the voltage between a pair of latch output terminals is within the predetermined range is larger than the bias current of the case in which the voltage between the pair of latch output terminals falls outside of the predetermined range. COPYRIGHT: (C)2011,JPO&INPIT
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