| 摘要 |
PROBLEM TO BE SOLVED: To provide a differential emitter coupling logic circuit which further lower the power supply voltage, compared with the conventional art. SOLUTION: A typical configuration of the differential emitter coupling logic circuit has: a first differential amplification circuit 10 and a second differential amplification circuit 20 which constitute an emitter coupled pair; a current switch 30 which selectively lowers collector voltage of each transistor Q1, Q2, Q7, Q8 of the first and second differential amplification circuits 10, 20; and an output stage 50. The output stage 50 is an emitter coupling pair. On the inverting input side of the emitter coupling pair, the two transistors Q9, Q10 are connected in parallel, and in those transistors, inverting side outputs of the first and second differential amplification circuits 10, 20 are input to the bases. On the non-inverting input side of the emitter coupled pair, the two transistors Q11, Q12 are connected in parallel, and in those transistors, non-inverting side outputs of the first and second differential amplification circuits are input to the bases. COPYRIGHT: (C)2011,JPO&INPIT
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