A power limiting circuit includes: a maximum value prediction filter section (MVPFS) interpolating data of one branched digital input signal; a maximum value detection section detecting maximum value of an output of the MVPFS and a time detection position thereof every constant period; a threshold subtraction section subtracting a threshold from detected maximum value and outputting a peak signal (zero when the subtraction result is negative); a coefficient selection section weighting the peak signal according to time detection position; a complex filter section limiting the weighted peak signal within a band of the input signal; a filter coefficient calculation section calculating filter coefficients of the complex filter section; a delay adjustment section delaying another of the branched input signals by a time period required for calculating the band-limited peak signal; and a subtraction section subtracting the band-limited peak signal from the other of the branched input signals subjected to delay.
申请公布号
US2011227628(A1)
申请公布日期
2011.09.22
申请号
US200913131967
申请日期
2009.12.17
申请人
NEC CORPORATION;HITACHI KOKUSAI ELECTRIC INC.
发明人
SATO HIROTAKA;KONO KIMIHIKO;DOI YOSHIAKI;KUSHIOKA YOICHI