| 摘要 |
<p>In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared.</p> |
