| 摘要 |
Disclosed is a data processing system 2 with processing circuitry 8, 10, 12 and as a bank of 64-bit registers 6. An instruction decoder 14 decodes arithmetic and logical instructions specifying arithmetic and logical operations to be performed upon operands stored in the 64-bit registers. The logical instructions have an operand size field SF specifying the size of the operands ie 64-bit or 32-bit operands. Each 64-bit register stores either a single 64-bit operand or a single 32-bit operand. For a given arithmetic or logical instruction either all of the operands are 64-bit operands or all are 32-bit operands. The circuitry may have a plurality of hierarchy of exception levels such that, if a switch is made to a lower exception level, then a check is made as to size of the previous write to the register being used. If the write was a 64-bit write, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.
|
