| 摘要 |
The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's.
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