PROCESSOR SYSTEM COMPRISING A LOW-POWER TRACE CACHE AND A COMMAND SET PREDICTOR

摘要

The present invention relates to a processor system, and more particularly, to a processor system comprising: a branch predictor; a low-power trace cache in which a plurality of command sets are stored, wherein one command set consists of commands predicted to not be branched; and a command set predictor which predicts a command set to be executed next, and prevents a processor core from accessing the branch predictor and a main command cache during the fetching of one command set.