发明名称 METHOD OF TESTING SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To detect minute defect existing in a PMOS load transistor of an SRAM (Static Random Access Memory) memory cell without extremely increasing circuit area and at high speed. SOLUTION: There is disclosed a method of testing a semiconductor memory device, including: a memory cell 10; first and second bit lines BLT and BLB connected to the memory cell 10; and a word line WL connected to the memory cell 10. The method includes: a first step of discharging the first and second bit lines BLT and BLB; a second step of setting the first bit line BLT to ground voltage while bringing the second bit line BLB into a floating state after the first step; and a third step of setting the word line WL to a potential higher than ground voltage after the second step. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011181142(A) 申请公布日期 2011.09.15
申请号 JP20100044393 申请日期 2010.03.01
申请人 NEC CORP 发明人 MORITA YASUHIRO;NOSE KOICHI
分类号 G11C29/06 主分类号 G11C29/06
代理机构 代理人
主权项
地址