发明名称 CLOCK CONTROL SIGNAL GENERATION CIRCUIT, CLOCK SELECTOR AND DATA PROCESSING DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a technique for performing high-speed switching between clock signals different in frequency. <P>SOLUTION: This clock control signal generation circuit (101) forms a control signal for clock switching in a clock selector performing the switching between a plurality of clock signals including a first clock signal based on a first clock stop permission signal, a second clock stop permission signal, and a clock resumption permission signal. The clock control signal generation circuit includes a before-switching clock processing part (102) and an after-switching clock processing part (106). In each of the before-switching clock processing part and the after-switching clock processing part, a high-frequency clock processing part and a low-frequency clock processing part take partial charges of processing of the clock signals related to the switching to speed up the processing. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011180736(A) 申请公布日期 2011.09.15
申请号 JP20100042771 申请日期 2010.02.26
申请人 RENESAS ELECTRONICS CORP 发明人 NARA YOSHIKAZU;TAKAHASHI YASUHIKO
分类号 G06F1/06;H03K5/00 主分类号 G06F1/06
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