| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a boosting circuit capable of reducing a chip area of a semiconductor chip. <P>SOLUTION: A boosting circuit 100 includes N (N is a natural number of 2 or more) capacitive elements (capacitive elements C0-C3). A K-th (1<K<N, K is a natural number) capacitive element (the capacitive element C2) among the N capacitive elements receives a (K-1)th boosted voltage boosted by a (K-1)th capacitive element (the capacitive element C1), and generates a K-th boosted voltage obtained by further boosting the (K-1)th boosted voltage to supply to a (K+1)th capacitive element (the capacitive element C3). An N-th boosted voltage is generated from one end (an output terminal OUT) of an N-th capacitive element. Among the N capacitive elements, at least one capacitive element (the capacitive elements C0 and C1) is formed in a second chip (a semiconductor chip CHIP1) different from a first chip (a semiconductor chip CHIP2) in which other capacitive elements (the capacitive elements C2 and C3) are formed, wherein the first and second chips are laminated with each other. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
