发明名称 METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS
摘要 A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad.
申请公布号 US2011223721(A1) 申请公布日期 2011.09.15
申请号 US201113081227 申请日期 2011.04.06
申请人 CHO NAMJU;CHI HEEJO;SHIN HANGIL 发明人 CHO NAMJU;CHI HEEJO;SHIN HANGIL
分类号 H01L21/56 主分类号 H01L21/56
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