发明名称 |
SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND DOPANT DIFFUSION RETARDING IMPLANTS AND RELATED METHODS |
摘要 |
<p>A semiconductor device (100) may include a substrate (101) and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel (125) including a plurality of stacked groups of layers, a source (102) and a drain (103) adjacent the superlattice channel, and a gate (106) adjacent the superlattice channel. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non - semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first dopant may be in at least one region adjacent at least one of the source and drain, and a second dopant may also be in the at least one region. The second dopant may be different than the first dopant and reduce diffusion thereof.</p> |
申请公布号 |
WO2011112574(A1) |
申请公布日期 |
2011.09.15 |
申请号 |
WO2011US27535 |
申请日期 |
2011.03.08 |
申请人 |
MEARS TECHNOLOGIES, INC;RAO, KALIPATNAM |
发明人 |
RAO, KALIPATNAM |
分类号 |
H01L21/265;H01L29/10;H01L29/15;H01L29/78 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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